In a conventional interconnect pattern formation process, a hard mask layer is first formed over the ILD layer in which an interconnect pattern is to be formed, and a photo- or electron beam-sensitive resist layer is then coated on top of the hard mask layer. The resist layer is imaged with photolithography or electron beam lithography, followed by developing the lithographic image into a corresponding pattern in the resist layer. Due to the collapsible nature of the organic resist layer during the image developing process, the aspect ratio of the resist pattern (i.e., thickness or height of the resist pattern verses its width) needs to be not more than about 2:1. For example, for 60 nm resist features, the maximum resist layer thickness is about 120 nm. Higher aspect ratio for the resist pattern is desirable for subsequent pattern transfer, i.e., a thicker resist layer provides more protection for the masked regions in the underlying layers, but it can lead to undesirable collapse in the resist layer during the image developing process.
Pattern transfer from the resist layer to the ILD layer typically involves two steps. First, the pattern is transferred from the resist layer into the hard mask layer. The hard mask layer performs dual functions, i.e., it maintains or enhances the aspect ratio of the pattern to be transferred at one hand, and on the other hand, it forms a stop layer for subsequent chemical mechanical polishing (CMP) of the metal wirings. Next, the pattern is transferred from the hard mask layer into the ILD layer.
The hard mask layer is employed during the pattern transfer process because the organic resist material is not suitable for direct image transfer into the ILD layer by RIE. Therefore, by first transferring the pattern from the resist layer to the hard mask layer in a chemical environment that is compatible with resist processing, specially selected chemicals that are not compatible with resist processing can subsequently be used for patterning the ILD layer, resulting in better image profile and improved aspect ratio for the metal wirings.
As complementary metal oxide semiconductor (CMOS) device scaling continues from 90 nm node and 65 nm node to 45 nm node and beyond, the overall interconnect dimension shrinks accordingly from 105 nm and 80 nm to 60 nm and below. The overall dimension reduction imposes significant limitations on the dimensions of the resist patterns.
On one hand, the overall dimension reduction in semiconductor devices leads not only to reduction in the line width of the interconnect patterns, but also to reduction in the line spacing between such interconnect patterns. For positive resists, the width of the resist pattern is determined by the line spacing between the interconnect patterns to be formed. Therefore, the overall dimension reduction in semiconductor devices causes reduction in the width of the resist patterns. However, as mentioned hereinabove, the aspect ratio of the resist pattern (i.e., thickness or height of the resist pattern verses its width) needs to be maintained at not more than about 2:1, in order to prevent resist pattern collapse during the image developing process. Thus, the resist thickness needs to be reduced correspondingly in the sub-60 nm node devices, in order to prevent structural collapse in the resist layer.
On the other hand, the patterned resist layer must have a sufficient thickness in order to provide effective mask for the underlying dielectric layers and to prevent the masked region of the underlying dielectric layers from being damaged during subsequent pattern transfer. Typically, the thicker the underlying dielectric layers, the longer the pattern transfer process takes, and the thicker the patterned resist has to be.
However, there are several non-scalable factors in the interconnect scaling that add to the thicknesses of the underlying dielectric layer(s). For example, different layers of interlevel dielectric (ILD) materials in the CMOS device structures are typically capped by interlevel capping layers. These interlevel capping layers function to maintain the structural, processing, and environmental integrity of the ILD layers, and they each have a layer thickness ranging from about 300 Å to about 500 Å, which is not scalable. For another example, the metal wirings in each ILD layer are typically formed over a metal liner, which provides good adhesion between the metal wirings and the ILD surface, prevents oxidation of the metal wirings and avoids diffusion of metal ions into the ILD material. The metal liner has a layer thickness ranging from about 100 Å to about 200 Å, which is also not scalable. For a further example, the metal wirings in each ILD layer need to be capped by an interconnect capping layer, which functions to seal the top surface of the metal wirings and concurrently form a bottom layer for subsequent deposition of additional layers thereabove. The interconnect capping layer typically has a layer thickness ranging from about 300 Å to about 500 Å that is further not scalable. Such non-scalable factors as illustrated hereinabove significantly limit possible reduction in the depth of the underlying dielectric layers. For successful transfer of the resist pattern onto such relatively thick underlying dielectric layers, the patterned resist must have a thickness sufficient to endure the prolonged pattern transfer process and to protect the masked regions of the underlying dielectric layers.
Such limitations, which are placed on the resist pattern thickness by the overall semiconductor dimension scaling on one hand and by the non-scalable factors in the dielectric depth on the other hand, in turn limit the possible choices of the hard mask structures that can be used for pattern transfer from the resist layer to the underlying ILD layers.
To accommodate the thickness limitations on the resist patterns, two hard mask structures have been conventionally used for forming the 90 nm node structures, which include the TaN-based metal hard mask (MHM) structure and the low temperature oxide-based (LTO-based) hard mask structure containing a near-frictionless carbon layer (typically referred to as NFC, which is a hydrogenated diamond-like carbon film that is commercially available from Japan Synthetic Rubber).
The TaN-based MHM structure contains a complex stack of layers that each performs a different function. First, a silicon-based anti-reflection coating (SiARC) layer is provided directly under the resist layer to absorb the lithographic light during the resist-imaging step and to prevent reflection of the light back into the resist layer. The SiARC layer further enhances adhesion between the TaN MHM layer and the resist layer. Second, a TaN layer with a high nitrogen content is provided under the SiARC layer as the metal hard mask layer, which also provides optical transparency for optical overlay. Third, a diamond-like carbon (DLC) layer is provided under the TaN layer as a CMP stop layer. Finally, an optional oxide layer can be formed above the ILD structure by a tetraethylorthosilicate (TEOS)-based process to provide an adhesion-enhancing layer for the TaN-based MHM structure and an oxygen barrier layer for the ILD structure.
In a typical TaN-based pattern transferring process, a resist layer is first applied onto the SiARC layer and then developed by photo- or electron beam-based lithography to form a desired pattern therein. The pattern in the resist layer is transferred to into the SiARC layer, the TaN MHM layer, and the DLC layer by RIE techniques. During the RIE process, the resist layer is consumed, and the SiARC/TaN-MHM/DLC stack is subsequently used as hard mask to transfer the pattern further into the ILD layer.
Pattern damage may occur during the pattern transfer from the SiARC/TaN-MHM/DLC hard mask stack to the ILD layer. Since the TaN MHM layer is not thick enough for protecting the masked region of the ILD layer during the RIE process, a highly polymerizable component (such as CH3F) is added during the RIE process to prevent the TaN MHM layer from being eroded too soon. However, the polymer layer formed by such a polymerizable component accumulates on sidewalls of the pattern to be transferred, leading to significant reduction in the critical dimension (CD) of the transferred pattern as well as increased roughness on the surfaces of the transferred pattern. Typical CD reduction resulting from the TaN-based pattern transferring process may amount to about 25 nm. The CD reduction not only significantly reduces the useful size of metal wirings in the 90 nm node and 65 nm node devices, but also leads to complete pattern transfer failure for the 45 nm node devices.
A common approach in solving the CD reduction problem is to increase the line width for compensating the line width reduction occurred during the RIE process. However, the increased line width causes corresponding reduction in the line spacing for a given device density, and the reduced line spacing in turn leads to reduced resist width and increased resist aspect ratio. Consequently, this approach inevitably leads to resist collapse in 45 nm node devices or sub-45 nm node devices (where the device density is very high) and therefore cannot be a viable process remedy for such devices.
The LTO-based hard mask structure also contains a complex stack of layers, including, from top to the bottom, a SiARC layer for anti-reflection and adhesion-enhancement, a LTO hard mask layer, and a NFC secondary pattern transfer layer. In a typical LTO-based pattern transferring process, a resist layer is applied onto the SiARC layer and developed by photo- or electron beam-based lithography to form a desired pattern therein. The pattern in the resist layer is then transferred to into the SiARC layer and the LTO hard mask layer by a first RIE step. Subsequently, the pattern is transferred to the NFC layer by a second RIE step.
The thickness of the NFC layer is chosen so that the combined thickness of the SiARC/LTO/NFC stack is sufficient to function as a hard mask to protect the masked region of the underlying ILD layer during the pattern transfer. Since the NFC secondary pattern transfer layer contains organic CH, its removal typically requires an oxygen-based RIE step. For dense ILD materials with medium to high dielectric constants (k), the LTO/NFC-based pattern transferring process is suitable because such dense ILD materials are resistant to oxygen-based RIE damages. However, when used with low-k or ultra low-k ILD materials, the LTO/NFC-based pattern transferring process may result in significant pattern damages (which can amount to a 25 nm increase in the critical dimension of the pattern transferred), because the low-k or ultra low-k ILD materials are particularly vulnerable to attacks by oxygen-based RIE.
There is therefore a continuing need for improved pattern transfer methods and improved hard mask stacks that can be used for transferring resist pattern into low-k or ultra low-k ILD materials.